This white paper describes the functionality of user defined fault models (UDFM), including gate exhaustive UDFM and cell-aware UDFM, and the effectiveness of lowering DPM in devices. To achieve today ...

The IDDQ test relies on measuring the supply current (I DD) of an IC’s quiescent state, when the circuit isn’t switching and inputs are held at static values. Test patterns are used to place the ...

ATPG targets faults at IC-gate boundaries, but 50% of defects are located within cells. Learn how cell-aware ATPG and user-defined fault models help to ferret out these hard-to-squash bugs.

A different set of fault models and testing techniques is required for memory blocks vs. logic. MBIST algorithms that are used to detect faults inside memory are based upon these fault models. This ...