The IDDQ test relies on measuring the supply current (I DD) of an IC’s quiescent state, when the circuit isn’t switching and inputs are held at static values. Test patterns are used to place the ...

ATPG targets faults at IC-gate boundaries, but 50% of defects are located within cells. Learn how cell-aware ATPG and user-defined fault models help to ferret out these hard-to-squash bugs.

To compete in the fast-growing market for automotive ICs, semiconductor companies need to address new challenges across the entire design flow. To meet the ISO 26262 goal of zero defective parts per ...