Yahoo Finance

Verific's SystemVerilog, VHDL Parsers Chosen by Flexras Technologies to Serve as Front End for FPGA-Based Prototyping Tool

ALAMEDA, CA--(Marketwired - Aug 5, 2014) - Verific Design Automation today announced Flexras Technologies, provider of high-performance partitioning software, has implemented its industry-standard, ...
Design-Reuse

Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements

Aldec’s Active-HDL™ enables FPGA designers to take full advantage of the many features within the latest revision to VHDL and helps improve design verification efficiency. Henderson, NV – January 20, ...
Yahoo Finance

Menta Follows FPGA Leaders by Selecting Verific for its SystemVerilog, VHDL Front End

ALAMEDA, CA--(Marketwired - Jul 2, 2014) - Verific Design Automation today announced Menta® selected its industry-standard, IEEE-compliant SystemVerilog and VHDL parsers to serve as the front end to ...
Semiconductor Engineering

FPGA VHDL Verification

This is actually possible – and with an average efficiency improvement of 20% to 50% for medium to high complexity FPGAs. Less for data path oriented designs and more for control or protocol oriented ...
mccormick.northwestern.edu

COMP_ENG 355: ASIC and FPGA Design

This course will introduce students to practical design methodologies for developing applications for FPGAs and ASICs. You will learn the fundamentals for FPGA and ASIC design through software coding ...
Hackaday

FPGA Snake Game Uses No VHDL At All

We’re really not supposed to start a feature like this; but this hack is awesome. It’s a game of Snake implemented by an FPGA dev board. It uses a 16×16 LED matrix as the display and an SNES ...
Hackaday

Xilinx FPGAs In C For Free

When you think of developing with FPGAs, you usually think of writing Verilog or VHDL. However, there’s been a relatively recent trend to use C to describe what an FPGA should do and have tools that ...
EDN

Product Update: FPGA and PLD Design Tools

The ACTgen Macro Builder is a parameterized macro function generator that enables users to construct highly efficient counters, adders, and other structured blocks. Developed as a productivity and ...
EDN

VHDL 101 – Getting Started

When you first get started with VHDL, a little bit of setting up needs to be done before you can really sink your teeth in. This should not put you off, however, as you only have to do this the once.
Yahoo Finance

Menta Follows FPGA Leaders by Selecting Verific for its SystemVerilog, VHDL Front End

ALAMEDA, CA--(Marketwired - Jul 2, 2014) - Verific Design Automation today announced Menta® selected its industry-standard, IEEE-compliant SystemVerilog and VHDL parsers to serve as the front end to ...