Electronic Design

Understanding Cell-Aware ATPG And User-Defined Fault Models

ATPG targets faults at IC-gate boundaries, but 50% of defects are located within cells. Learn how cell-aware ATPG and user-defined fault models help to ferret out these hard-to-squash bugs.
Semiconductor Engineering

Transformer Model Based Clustering Methodology For Standard Cell Layout Automation (Nvidia)

A new technical paper titled “Novel Transformer Model Based Clustering Method for Standard Cell Design Automation” was published by researchers at Nvidia. “Standard cells are essential components of ...
EDN

Design-specific standard cells yield custom performance

A key limiting factor in standard cell based IC design is the standard cell library itself. This is because standard cell libraries don't offer the necessary variety of cells — in terms of ...
Electronic Design

Standard-Cell Optimization Flow Pumps Yield, Tightens Area

Manual and automated IC-layout tools are integrated in the PEYE Yield Finder analysis software. The combined yield-driven, standard-cell, design optimization flow facilitates the application of design ...
Semiconductor Engineering

5 Novel Layout Design Methodologies For The 3nm Nanosheet FET Library (Samsung, KNU)

A new technical paper titled “Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node” was published by researchers at Samsung ...